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v2.1.1 (RP2040)
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xip.h
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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#ifndef _HARDWARE_STRUCTS_XIP_H
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#define _HARDWARE_STRUCTS_XIP_H
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#include "
hardware/address_mapped.h
"
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#include "hardware/regs/xip.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_xip
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/xip.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
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typedef
struct
{
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_REG_(XIP_CTRL_OFFSET)
// XIP_CTRL
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// Cache control
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// 0x00000008 [3] POWER_DOWN (0) When 1, the cache memories are powered down
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// 0x00000002 [1] ERR_BADWRITE (1) When 1, writes to any alias other than 0x0 (caching,...
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// 0x00000001 [0] EN (1) When 1, enable the cache
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io_rw_32 ctrl;
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_REG_(XIP_FLUSH_OFFSET)
// XIP_FLUSH
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// Cache Flush control
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// 0x00000001 [0] FLUSH (0) Write 1 to flush the cache
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io_wo_32 flush;
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_REG_(XIP_STAT_OFFSET)
// XIP_STAT
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// Cache Status
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// 0x00000004 [2] FIFO_FULL (0) When 1, indicates the XIP streaming FIFO is completely full
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// 0x00000002 [1] FIFO_EMPTY (1) When 1, indicates the XIP streaming FIFO is completely empty
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// 0x00000001 [0] FLUSH_READY (0) Reads as 0 while a cache flush is in progress, and 1 otherwise
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io_ro_32
stat
;
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_REG_(XIP_CTR_HIT_OFFSET)
// XIP_CTR_HIT
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// Cache Hit counter
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// 0xffffffff [31:0] CTR_HIT (0x00000000) A 32 bit saturating counter that increments upon each...
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io_rw_32 ctr_hit;
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_REG_(XIP_CTR_ACC_OFFSET)
// XIP_CTR_ACC
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// Cache Access counter
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// 0xffffffff [31:0] CTR_ACC (0x00000000) A 32 bit saturating counter that increments upon each...
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io_rw_32 ctr_acc;
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_REG_(XIP_STREAM_ADDR_OFFSET)
// XIP_STREAM_ADDR
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// FIFO stream address
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// 0xfffffffc [31:2] STREAM_ADDR (0x00000000) The address of the next word to be streamed from flash...
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io_rw_32 stream_addr;
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_REG_(XIP_STREAM_CTR_OFFSET)
// XIP_STREAM_CTR
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// FIFO stream control
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// 0x003fffff [21:0] STREAM_CTR (0x000000) Write a nonzero value to start a streaming read
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io_rw_32 stream_ctr;
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_REG_(XIP_STREAM_FIFO_OFFSET)
// XIP_STREAM_FIFO
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// FIFO stream data
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// 0xffffffff [31:0] STREAM_FIFO (0x00000000) Streamed data is buffered here, for retrieval by the system DMA
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io_ro_32 stream_fifo;
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}
xip_ctrl_hw_t
;
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#define xip_ctrl_hw ((xip_ctrl_hw_t *)XIP_CTRL_BASE)
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static_assert
(
sizeof
(
xip_ctrl_hw_t
) == 0x0020,
""
);
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#endif
// _HARDWARE_STRUCTS_XIP_H
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address_mapped.h
stat
Definition
stat.h:12
xip_ctrl_hw_t
Definition
xip.h:26