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pwm.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
8#ifndef _HARDWARE_STRUCTS_PWM_H
9#define _HARDWARE_STRUCTS_PWM_H
10
16#include "hardware/regs/pwm.h"
17
18// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pwm
19//
20// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
21// _REG_(x) will link to the corresponding register in hardware/regs/pwm.h.
22//
23// Bit-field descriptions are of the form:
24// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
25
26typedef struct {
27 _REG_(PWM_CH0_CSR_OFFSET) // PWM_CH0_CSR
28 // Control and status register
29 // 0x00000080 [7] PH_ADV (0) Advance the phase of the counter by 1 count, while it is running
30 // 0x00000040 [6] PH_RET (0) Retard the phase of the counter by 1 count, while it is running
31 // 0x00000030 [5:4] DIVMODE (0x0)
32 // 0x00000008 [3] B_INV (0) Invert output B
33 // 0x00000004 [2] A_INV (0) Invert output A
34 // 0x00000002 [1] PH_CORRECT (0) 1: Enable phase-correct modulation
35 // 0x00000001 [0] EN (0) Enable the PWM channel
36 io_rw_32 csr;
37
38 _REG_(PWM_CH0_DIV_OFFSET) // PWM_CH0_DIV
39 // INT and FRAC form a fixed-point fractional number
40 // 0x00000ff0 [11:4] INT (0x01)
41 // 0x0000000f [3:0] FRAC (0x0)
42 io_rw_32 div;
43
44 _REG_(PWM_CH0_CTR_OFFSET) // PWM_CH0_CTR
45 // Direct access to the PWM counter
46 // 0x0000ffff [15:0] CH0_CTR (0x0000)
47 io_rw_32 ctr;
48
49 _REG_(PWM_CH0_CC_OFFSET) // PWM_CH0_CC
50 // Counter compare values
51 // 0xffff0000 [31:16] B (0x0000)
52 // 0x0000ffff [15:0] A (0x0000)
53 io_rw_32 cc;
54
55 _REG_(PWM_CH0_TOP_OFFSET) // PWM_CH0_TOP
56 // Counter wrap value
57 // 0x0000ffff [15:0] CH0_TOP (0xffff)
58 io_rw_32 top;
60
61typedef struct {
62 _REG_(PWM_INTE_OFFSET) // PWM_INTE
63 // Interrupt Enable
64 // 0x00000080 [7] CH7 (0)
65 // 0x00000040 [6] CH6 (0)
66 // 0x00000020 [5] CH5 (0)
67 // 0x00000010 [4] CH4 (0)
68 // 0x00000008 [3] CH3 (0)
69 // 0x00000004 [2] CH2 (0)
70 // 0x00000002 [1] CH1 (0)
71 // 0x00000001 [0] CH0 (0)
72 io_rw_32 inte;
73
74 _REG_(PWM_INTF_OFFSET) // PWM_INTF
75 // Interrupt Force
76 // 0x00000080 [7] CH7 (0)
77 // 0x00000040 [6] CH6 (0)
78 // 0x00000020 [5] CH5 (0)
79 // 0x00000010 [4] CH4 (0)
80 // 0x00000008 [3] CH3 (0)
81 // 0x00000004 [2] CH2 (0)
82 // 0x00000002 [1] CH1 (0)
83 // 0x00000001 [0] CH0 (0)
84 io_rw_32 intf;
85
86 _REG_(PWM_INTS_OFFSET) // PWM_INTS
87 // Interrupt status after masking & forcing
88 // 0x00000080 [7] CH7 (0)
89 // 0x00000040 [6] CH6 (0)
90 // 0x00000020 [5] CH5 (0)
91 // 0x00000010 [4] CH4 (0)
92 // 0x00000008 [3] CH3 (0)
93 // 0x00000004 [2] CH2 (0)
94 // 0x00000002 [1] CH1 (0)
95 // 0x00000001 [0] CH0 (0)
96 io_ro_32 ints;
98
99typedef struct {
100 pwm_slice_hw_t slice[8];
101
102 _REG_(PWM_EN_OFFSET) // PWM_EN
103 // This register aliases the CSR_EN bits for all channels
104 // 0x00000080 [7] CH7 (0)
105 // 0x00000040 [6] CH6 (0)
106 // 0x00000020 [5] CH5 (0)
107 // 0x00000010 [4] CH4 (0)
108 // 0x00000008 [3] CH3 (0)
109 // 0x00000004 [2] CH2 (0)
110 // 0x00000002 [1] CH1 (0)
111 // 0x00000001 [0] CH0 (0)
112 io_rw_32 en;
113
114 _REG_(PWM_INTR_OFFSET) // PWM_INTR
115 // Raw Interrupts
116 // 0x00000080 [7] CH7 (0)
117 // 0x00000040 [6] CH6 (0)
118 // 0x00000020 [5] CH5 (0)
119 // 0x00000010 [4] CH4 (0)
120 // 0x00000008 [3] CH3 (0)
121 // 0x00000004 [2] CH2 (0)
122 // 0x00000002 [1] CH1 (0)
123 // 0x00000001 [0] CH0 (0)
124 io_rw_32 intr;
125
126 union {
127 struct {
128 _REG_(PWM_INTE_OFFSET) // PWM_INTE
129 // Interrupt Enable
130 // 0x00000080 [7] CH7 (0)
131 // 0x00000040 [6] CH6 (0)
132 // 0x00000020 [5] CH5 (0)
133 // 0x00000010 [4] CH4 (0)
134 // 0x00000008 [3] CH3 (0)
135 // 0x00000004 [2] CH2 (0)
136 // 0x00000002 [1] CH1 (0)
137 // 0x00000001 [0] CH0 (0)
138 io_rw_32 inte;
139
140 _REG_(PWM_INTF_OFFSET) // PWM_INTF
141 // Interrupt Force
142 // 0x00000080 [7] CH7 (0)
143 // 0x00000040 [6] CH6 (0)
144 // 0x00000020 [5] CH5 (0)
145 // 0x00000010 [4] CH4 (0)
146 // 0x00000008 [3] CH3 (0)
147 // 0x00000004 [2] CH2 (0)
148 // 0x00000002 [1] CH1 (0)
149 // 0x00000001 [0] CH0 (0)
150 io_rw_32 intf;
151
152 _REG_(PWM_INTS_OFFSET) // PWM_INTS
153 // Interrupt status after masking & forcing
154 // 0x00000080 [7] CH7 (0)
155 // 0x00000040 [6] CH6 (0)
156 // 0x00000020 [5] CH5 (0)
157 // 0x00000010 [4] CH4 (0)
158 // 0x00000008 [3] CH3 (0)
159 // 0x00000004 [2] CH2 (0)
160 // 0x00000002 [1] CH1 (0)
161 // 0x00000001 [0] CH0 (0)
162 io_rw_32 ints;
163 };
164 pwm_irq_ctrl_hw_t irq_ctrl[1];
165 };
166} pwm_hw_t;
167
168#define pwm_hw ((pwm_hw_t *)PWM_BASE)
169static_assert(sizeof (pwm_hw_t) == 0x00b4, "");
170
171#endif // _HARDWARE_STRUCTS_PWM_H
172
Definition pwm.h:99
Definition pwm.h:61
Definition pwm.h:26