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pio.h
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1/*
2 * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef _HARDWARE_PIO_H
8#define _HARDWARE_PIO_H
9
10#include "pico.h"
12#include "hardware/structs/pio.h"
13#include "hardware/gpio.h"
14#include "hardware/regs/dreq.h"
15#include "hardware/pio_instructions.h"
16
17// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_PIO, Enable/disable assertions in the hardware_pio module, type=bool, default=0, group=hardware_pio
18#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_PIO
19#ifdef PARAM_ASSERTIONS_ENABLED_PIO // backwards compatibility with SDK < 2.0.0
20#define PARAM_ASSERTIONS_ENABLED_HARDWARE_PIO PARAM_ASSERTIONS_ENABLED_PIO
21#else
22#define PARAM_ASSERTIONS_ENABLED_HARDWARE_PIO 0
23#endif
24#endif
25
26// PICO_CONFIG: PICO_PIO_VERSION, PIO hardware version, type=int, default=0 on RP2040 and 1 on RP2350, group=hardware_pio
27#ifndef PICO_PIO_VERSION
28#if PIO_GPIOBASE_BITS
29#define PICO_PIO_VERSION 1
30#else
31#define PICO_PIO_VERSION 0
32#endif
33#endif
34
35// PICO_CONFIG: PICO_PIO_CLKDIV_ROUND_NEAREST, True if floating point PIO clock divisors should be rounded to the nearest possible clock divisor rather than rounding down, type=bool, default=PICO_CLKDIV_ROUND_NEAREST, group=hardware_pio
36#ifndef PICO_PIO_CLKDIV_ROUND_NEAREST
37#define PICO_PIO_CLKDIV_ROUND_NEAREST PICO_CLKDIV_ROUND_NEAREST
38#endif
39
99#ifdef __cplusplus
100extern "C" {
101#endif
102
103static_assert(PIO_SM0_SHIFTCTRL_FJOIN_RX_LSB == PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB + 1, "");
104
112#if PICO_PIO_VERSION > 0
113 PIO_FIFO_JOIN_TXGET = 4,
114 PIO_FIFO_JOIN_TXPUT = 8,
115 PIO_FIFO_JOIN_PUTGET = 12,
116#endif
117};
118
123 STATUS_TX_LESSTHAN = 0,
124 STATUS_RX_LESSTHAN = 1,
125#if PICO_PIO_VERSION > 0
126 STATUS_IRQ_SET = 2
127#endif
128};
129
130typedef pio_hw_t *PIO;
131
138#define pio0 pio0_hw
139
146#define pio1 pio1_hw
147
148#if NUM_PIOS > 2
155#define pio2 pio2_hw
156#endif
157
158#if PICO_PIO_VERSION > 0
159#ifndef PICO_PIO_USE_GPIO_BASE
160// PICO_CONFIG: PICO_PIO_USE_GPIO_BASE, Enable code for handling more than 32 PIO pins, type=bool, default=true when supported and when the device has more than 32 pins, group=hardware_pio
161#define PICO_PIO_USE_GPIO_BASE ((NUM_BANK0_GPIOS) > 32)
162#endif
163#endif
164
173#ifndef PIO_NUM
174static_assert(PIO1_BASE - PIO0_BASE == (1u << 20), "hardware layout mismatch");
175#if NUM_PIOS > 2
176static_assert(PIO2_BASE - PIO0_BASE == (2u << 20), "hardware layout mismatch");
177#endif
178#define PIO_NUM(pio) (((uintptr_t)(pio) - PIO0_BASE) >> 20)
179#endif
180
189#ifndef PIO_INSTANCE
190static_assert(PIO1_BASE - PIO0_BASE == (1u << 20), "hardware layout mismatch");
191#if NUM_PIOS > 2
192static_assert(PIO2_BASE - PIO0_BASE == (2u << 20), "hardware layout mismatch");
193#endif
194#define PIO_INSTANCE(instance) ((pio_hw_t *)(PIO0_BASE + (instance) * (1u << 20)))
195#endif
196
205#ifndef PIO_FUNCSEL_NUM
206#define PIO_FUNCSEL_NUM(pio, gpio) ((gpio_function_t) (GPIO_FUNC_PIO0 + PIO_NUM(pio)))
207#endif
208
218#ifndef PIO_DREQ_NUM
219static_assert(DREQ_PIO0_TX1 == DREQ_PIO0_TX0 + 1, "");
220static_assert(DREQ_PIO0_TX2 == DREQ_PIO0_TX0 + 2, "");
221static_assert(DREQ_PIO0_TX3 == DREQ_PIO0_TX0 + 3, "");
222static_assert(DREQ_PIO0_RX0 == DREQ_PIO0_TX0 + NUM_PIO_STATE_MACHINES, "");
223static_assert(DREQ_PIO1_TX0 == DREQ_PIO0_RX0 + NUM_PIO_STATE_MACHINES, "");
224static_assert(DREQ_PIO1_RX0 == DREQ_PIO1_TX0 + NUM_PIO_STATE_MACHINES, "");
225#if NUM_PIOS > 2
226static_assert(DREQ_PIO2_TX0 == DREQ_PIO1_RX0 + NUM_PIO_STATE_MACHINES, "");
227static_assert(DREQ_PIO2_RX0 == DREQ_PIO2_TX0 + NUM_PIO_STATE_MACHINES, "");
228#endif
229#define PIO_DREQ_NUM(pio, sm, is_tx) (DREQ_PIO0_TX0 + (sm) + (((is_tx) ? 0 : NUM_PIO_STATE_MACHINES) + PIO_NUM(pio) * (DREQ_PIO1_TX0 - DREQ_PIO0_TX0)))
230#endif
231
240#ifndef PIO_IRQ_NUM
241#define PIO_IRQ_NUM(pio, irqn) (PIO0_IRQ_0 + NUM_PIO_IRQS * PIO_NUM(pio) + (irqn))
242#endif
243
290typedef struct {
291 uint32_t clkdiv;
292 uint32_t execctrl;
293 uint32_t shiftctrl;
294 uint32_t pinctrl;
295#if PICO_PIO_USE_GPIO_BASE
296#define PINHI_ALL_PINCTRL_LSBS ((1u << PIO_SM0_PINCTRL_IN_BASE_LSB) | (1u << PIO_SM0_PINCTRL_OUT_BASE_LSB) | \
297 (1u << PIO_SM0_PINCTRL_SET_BASE_LSB) | (1u << PIO_SM0_PINCTRL_SIDESET_BASE_LSB))
298// note we put the out_special pin starting at bit 20
299#define PINHI_EXECCTRL_LSB 20
300static_assert( (1u << PINHI_EXECCTRL_LSB) > (PINHI_ALL_PINCTRL_LSBS * 0x1f), "");
301#define PINHI_ALL_PIN_LSBS ((1u << PINHI_EXECCTRL_LSB) |(1u << PIO_SM0_PINCTRL_IN_BASE_LSB) | (1u << PIO_SM0_PINCTRL_OUT_BASE_LSB) | \
302 (1u << PIO_SM0_PINCTRL_SET_BASE_LSB) | (1u << PIO_SM0_PINCTRL_SIDESET_BASE_LSB))
303 // each 5-bit field which would usually be used for the pin_base in pin_ctrl, is used for:
304 // 0b11111 - corresponding field not specified
305 // 0b00000 - pin is in range 0-15
306 // 0b00001 - pin is in range 16-31
307 // 0b00010 - pin is in range 32-47
308 uint32_t pinhi;
309#endif
311
312static inline void check_sm_param(__unused uint sm) {
313 valid_params_if(HARDWARE_PIO, sm < NUM_PIO_STATE_MACHINES);
314}
315
316static inline void check_sm_mask(__unused uint mask) {
317 valid_params_if(HARDWARE_PIO, mask < (1u << NUM_PIO_STATE_MACHINES));
318}
319
320static inline void check_pio_param(__unused PIO pio) {
321#if NUM_PIOS == 2
322 valid_params_if(HARDWARE_PIO, pio == pio0 || pio == pio1);
323#elif NUM_PIOS == 3
324 valid_params_if(HARDWARE_PIO, pio == pio0 || pio == pio1 || pio == pio2);
325#endif
326}
327
328static inline void check_pio_pin_param(__unused uint pin) {
329#if !PICO_PIO_USE_GPIO_BASE
330 invalid_params_if(HARDWARE_PIO, pin >= 32);
331#else
332 // pin base allows us to move up 16 pins at a time
333 invalid_params_if(HARDWARE_PIO, pin >= ((NUM_BANK0_GPIOS + 15u)&~15u));
334#endif
335}
336
345static inline void sm_config_set_out_pin_base(pio_sm_config *c, uint out_base) {
346 check_pio_pin_param(out_base);
347 c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_OUT_BASE_BITS) |
348 ((out_base & 31) << PIO_SM0_PINCTRL_OUT_BASE_LSB);
349#if PICO_PIO_USE_GPIO_BASE
350 c->pinhi = (c->pinhi & ~(31u << PIO_SM0_PINCTRL_OUT_BASE_LSB)) |
351 ((out_base >> 4) << PIO_SM0_PINCTRL_OUT_BASE_LSB);
352#endif
353}
354
363static inline void sm_config_set_out_pin_count(pio_sm_config *c, uint out_count) {
364 valid_params_if(HARDWARE_PIO, out_count <= 32);
365 c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_OUT_COUNT_BITS) |
366 (out_count << PIO_SM0_PINCTRL_OUT_COUNT_LSB);
367}
368
378static inline void sm_config_set_out_pins(pio_sm_config *c, uint out_base, uint out_count) {
379 sm_config_set_out_pin_base(c, out_base);
380 sm_config_set_out_pin_count(c, out_count);
381}
382
391static inline void sm_config_set_set_pin_base(pio_sm_config *c, uint set_base) {
392 check_pio_pin_param(set_base);
393 c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SET_BASE_BITS) |
394 ((set_base & 31) << PIO_SM0_PINCTRL_SET_BASE_LSB);
395#if PICO_PIO_USE_GPIO_BASE
396 c->pinhi = (c->pinhi & ~(31u << PIO_SM0_PINCTRL_SET_BASE_LSB)) |
397 ((set_base >> 4) << PIO_SM0_PINCTRL_SET_BASE_LSB);
398#endif
399}
400
409static inline void sm_config_set_set_pin_count(pio_sm_config *c, uint set_count) {
410 valid_params_if(HARDWARE_PIO, set_count <= 5);
411 c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SET_COUNT_BITS) |
412 (set_count << PIO_SM0_PINCTRL_SET_COUNT_LSB);
413}
414
424static inline void sm_config_set_set_pins(pio_sm_config *c, uint set_base, uint set_count) {
425 sm_config_set_set_pin_base(c, set_base);
426 sm_config_set_set_pin_count(c, set_count);
427}
428
437static inline void sm_config_set_in_pin_base(pio_sm_config *c, uint in_base) {
438 check_pio_pin_param(in_base);
439 c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_IN_BASE_BITS) |
440 ((in_base & 31) << PIO_SM0_PINCTRL_IN_BASE_LSB);
441#if PICO_PIO_USE_GPIO_BASE
442 c->pinhi = (c->pinhi & ~(31u << PIO_SM0_PINCTRL_IN_BASE_LSB)) |
443 ((in_base >> 4) << PIO_SM0_PINCTRL_IN_BASE_LSB);
444#endif
445}
446
455static inline void sm_config_set_in_pins(pio_sm_config *c, uint in_base) {
456 sm_config_set_in_pin_base(c, in_base);
457}
458
472static inline void sm_config_set_in_pin_count(pio_sm_config *c, uint in_count) {
473#if PICO_PIO_VERSION == 0
474 // can't be changed from 32 on PIO v0
475 ((void)c);
476 valid_params_if(HARDWARE_PIO, in_count == 32);
477#else
478 valid_params_if(HARDWARE_PIO, in_count && in_count <= 32);
479 c->shiftctrl = (c->shiftctrl & ~PIO_SM0_SHIFTCTRL_IN_COUNT_BITS) |
480 ((in_count & 0x1fu) << PIO_SM0_SHIFTCTRL_IN_COUNT_LSB);
481#endif
482}
483
492static inline void sm_config_set_sideset_pin_base(pio_sm_config *c, uint sideset_base) {
493 check_pio_pin_param(sideset_base);
494 c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SIDESET_BASE_BITS) |
495 ((sideset_base & 31) << PIO_SM0_PINCTRL_SIDESET_BASE_LSB);
496#if PICO_PIO_USE_GPIO_BASE
497 c->pinhi = (c->pinhi & ~(31u << PIO_SM0_PINCTRL_SIDESET_BASE_LSB)) |
498 ((sideset_base >> 4) << PIO_SM0_PINCTRL_SIDESET_BASE_LSB);
499#endif
500}
501
513static inline void sm_config_set_sideset_pins(pio_sm_config *c, uint sideset_base) {
514 sm_config_set_sideset_pin_base(c, sideset_base);
515}
516
525static inline void sm_config_set_sideset(pio_sm_config *c, uint bit_count, bool optional, bool pindirs) {
526 valid_params_if(HARDWARE_PIO, bit_count <= 5);
527 valid_params_if(HARDWARE_PIO, !optional || bit_count >= 1);
528 c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SIDESET_COUNT_BITS) |
529 (bit_count << PIO_SM0_PINCTRL_SIDESET_COUNT_LSB);
530 c->execctrl = (c->execctrl & ~(PIO_SM0_EXECCTRL_SIDE_EN_BITS | PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS)) |
531 (bool_to_bit(optional) << PIO_SM0_EXECCTRL_SIDE_EN_LSB) |
532 (bool_to_bit(pindirs) << PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB);
533}
534
548static inline void sm_config_set_clkdiv_int_frac8(pio_sm_config *c, uint32_t div_int, uint8_t div_frac8) {
549 static_assert(REG_FIELD_WIDTH(PIO_SM0_CLKDIV_INT) == 16, "");
550 invalid_params_if(HARDWARE_PIO, div_int >> 16);
551 invalid_params_if(HARDWARE_PIO, div_int == 0 && div_frac8 != 0);
552 static_assert(REG_FIELD_WIDTH(PIO_SM0_CLKDIV_FRAC) == 8, "");
553 c->clkdiv =
554 (((uint)div_frac8) << PIO_SM0_CLKDIV_FRAC_LSB) |
555 (((uint)div_int) << PIO_SM0_CLKDIV_INT_LSB);
556}
557
558// backwards compatibility
559static inline void sm_config_set_clkdiv_int_frac(pio_sm_config *c, uint16_t div_int, uint8_t div_frac8) {
560 sm_config_set_clkdiv_int_frac8(c, div_int, div_frac8);
561}
562
563static inline void pio_calculate_clkdiv8_from_float(float div, uint32_t *div_int, uint8_t *div_frac8) {
564 valid_params_if(HARDWARE_PIO, div >= 1 && div <= 65536);
565 const int frac_bit_count = REG_FIELD_WIDTH(PIO_SM0_CLKDIV_FRAC);
566#if PICO_PIO_CLKDIV_ROUND_NEAREST
567 div += 0.5f / (1 << frac_bit_count); // round to the nearest 1/256
568#endif
569 *div_int = (uint16_t)div;
570 // not a strictly necessary check, but if this changes, then this method should
571 // probably no longer be used in favor of one with a larger fraction
572 static_assert(REG_FIELD_WIDTH(PIO_SM0_CLKDIV_FRAC) == 8, "");
573 if (*div_int == 0) {
574 *div_frac8 = 0;
575 } else {
576 *div_frac8 = (uint8_t)((div - (float)*div_int) * (1u << frac_bit_count));
577 }
578}
579
580// backwards compatibility
581static inline void pio_calculate_clkdiv_from_float(float div, uint16_t *div_int16, uint8_t *div_frac8) {
582 uint32_t div_int;
583 pio_calculate_clkdiv8_from_float(div, &div_int, div_frac8);
584 *div_int16 = (uint16_t) div_int;
585}
586
602static inline void sm_config_set_clkdiv(pio_sm_config *c, float div) {
603 uint32_t div_int;
604 uint8_t div_frac8;
605 pio_calculate_clkdiv8_from_float(div, &div_int, &div_frac8);
606 sm_config_set_clkdiv_int_frac8(c, div_int, div_frac8);
607}
608
617static inline void sm_config_set_wrap(pio_sm_config *c, uint wrap_target, uint wrap) {
618 valid_params_if(HARDWARE_PIO, wrap < PIO_INSTRUCTION_COUNT);
619 valid_params_if(HARDWARE_PIO, wrap_target < PIO_INSTRUCTION_COUNT);
620 c->execctrl = (c->execctrl & ~(PIO_SM0_EXECCTRL_WRAP_TOP_BITS | PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS)) |
621 (wrap_target << PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB) |
622 (wrap << PIO_SM0_EXECCTRL_WRAP_TOP_LSB);
623}
624
631static inline void sm_config_set_jmp_pin(pio_sm_config *c, uint pin) {
632 check_pio_pin_param(pin);
633 c->execctrl = (c->execctrl & ~PIO_SM0_EXECCTRL_JMP_PIN_BITS) |
634 ((pin & 31) << PIO_SM0_EXECCTRL_JMP_PIN_LSB);
635#if PICO_PIO_USE_GPIO_BASE
636 c->pinhi = (c->pinhi & ~(31u << 20)) |
637 ((pin >> 4) << 20);
638#endif
639}
640
649static inline void sm_config_set_in_shift(pio_sm_config *c, bool shift_right, bool autopush, uint push_threshold) {
650 valid_params_if(HARDWARE_PIO, push_threshold <= 32);
651 c->shiftctrl = (c->shiftctrl &
652 ~(PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS |
653 PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS |
654 PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS)) |
655 (bool_to_bit(shift_right) << PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB) |
656 (bool_to_bit(autopush) << PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB) |
657 ((push_threshold & 0x1fu) << PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB);
658}
659
668static inline void sm_config_set_out_shift(pio_sm_config *c, bool shift_right, bool autopull, uint pull_threshold) {
669 valid_params_if(HARDWARE_PIO, pull_threshold <= 32);
670 c->shiftctrl = (c->shiftctrl &
671 ~(PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS |
672 PIO_SM0_SHIFTCTRL_AUTOPULL_BITS |
673 PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS)) |
674 (bool_to_bit(shift_right) << PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB) |
675 (bool_to_bit(autopull) << PIO_SM0_SHIFTCTRL_AUTOPULL_LSB) |
676 ((pull_threshold & 0x1fu) << PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB);
677}
678
685static inline void sm_config_set_fifo_join(pio_sm_config *c, enum pio_fifo_join join) {
686 valid_params_if(HARDWARE_PIO, join == PIO_FIFO_JOIN_NONE || join == PIO_FIFO_JOIN_TX || join == PIO_FIFO_JOIN_RX
687#if PICO_PIO_VERSION > 0
688 || join == PIO_FIFO_JOIN_TXPUT || join == PIO_FIFO_JOIN_TXGET || join == PIO_FIFO_JOIN_PUTGET
689#endif
690 );
691#if PICO_PIO_VERSION == 0
692 c->shiftctrl = (c->shiftctrl & (uint)~(PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS | PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS)) |
693 (((uint)join) << PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB);
694#else
695 c->shiftctrl = (c->shiftctrl & (uint)~(PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS | PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS |
696 PIO_SM0_SHIFTCTRL_FJOIN_RX_PUT_BITS | PIO_SM0_SHIFTCTRL_FJOIN_RX_GET_BITS)) |
697 (((uint)(join & 3)) << PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB) |
698 (((uint)(join >> 2)) << PIO_SM0_SHIFTCTRL_FJOIN_RX_GET_LSB);
699#endif
700}
701
710static inline void sm_config_set_out_special(pio_sm_config *c, bool sticky, bool has_enable_pin, uint enable_bit_index) {
711 c->execctrl = (c->execctrl &
712 (uint)~(PIO_SM0_EXECCTRL_OUT_STICKY_BITS | PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS |
713 PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS)) |
714 (bool_to_bit(sticky) << PIO_SM0_EXECCTRL_OUT_STICKY_LSB) |
715 (bool_to_bit(has_enable_pin) << PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB) |
716 ((enable_bit_index << PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB) & PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS);
717}
718
726static inline void sm_config_set_mov_status(pio_sm_config *c, enum pio_mov_status_type status_sel, uint status_n) {
727 valid_params_if(HARDWARE_PIO,
728 status_sel == STATUS_TX_LESSTHAN || status_sel == STATUS_RX_LESSTHAN
729#if PICO_PIO_VERSION > 0
730 || status_sel == STATUS_IRQ_SET
731#endif
732 );
733 c->execctrl = (c->execctrl
734 & ~(PIO_SM0_EXECCTRL_STATUS_SEL_BITS | PIO_SM0_EXECCTRL_STATUS_N_BITS))
735 | ((((uint)status_sel) << PIO_SM0_EXECCTRL_STATUS_SEL_LSB) & PIO_SM0_EXECCTRL_STATUS_SEL_BITS)
736 | ((status_n << PIO_SM0_EXECCTRL_STATUS_N_LSB) & PIO_SM0_EXECCTRL_STATUS_N_BITS);
737}
738
759 pio_sm_config c = {};
760#if PICO_PIO_USE_GPIO_BASE
761 c.pinhi = -1;
762#endif
764 sm_config_set_wrap(&c, 0, 31);
765 sm_config_set_in_shift(&c, true, false, 32);
766 sm_config_set_out_shift(&c, true, false, 32);
767 return c;
768}
769
780static inline uint pio_get_gpio_base(PIO pio) {
781#if PICO_PIO_VERSION > 0
782 return pio->gpiobase;
783#else
784 ((void)pio);
785 return 0;
786#endif
787}
788
789static inline void check_pio_pin_mask64(__unused PIO pio, __unused uint sm, __unused uint64_t pinmask) {
790 // check no pins are set in the mask which are incompatible with the pio
791#if PICO_PIO_USE_GPIO_BASE
792 valid_params_if(HARDWARE_PIO, (pinmask & ~(0xffffffffull << pio_get_gpio_base(pio))) == 0);
793#else
794 valid_params_if(HARDWARE_PIO, (pinmask & ~0xffffffffull) == 0);
795#endif
796}
797
809static inline int pio_sm_set_config(PIO pio, uint sm, const pio_sm_config *config) {
810 check_pio_param(pio);
811 check_sm_param(sm);
812 pio->sm[sm].clkdiv = config->clkdiv;
813 pio->sm[sm].shiftctrl = config->shiftctrl;
814#if PICO_PIO_USE_GPIO_BASE
815 uint used = (~config->pinhi >> 4) & PINHI_ALL_PIN_LSBS;
816 // configs that use pins 0-15
817 uint gpio_under_16 = (~config->pinhi) & (~config->pinhi >> 1) & used;
818 // configs that use pins 32-47
819 uint gpio_over_32 = (config->pinhi >> 1) & used;
820 uint gpio_base = pio_get_gpio_base(pio);
821 invalid_params_if_and_return(PIO, gpio_under_16 && gpio_base, PICO_ERROR_BAD_ALIGNMENT);
822 invalid_params_if_and_return(PIO, gpio_over_32 && !gpio_base, PICO_ERROR_BAD_ALIGNMENT);
823 // flip the top bit of any used (execctrl/pinctrl) values to turn:
824 // bit6(32) + 0-15 -> base(16) + 16-31
825 // bit6(0) + 16-31 -> base(16) + 0-15
826 static_assert(PINHI_EXECCTRL_LSB == 20, ""); // we use shifts to mask off bits below
827 pio->sm[sm].execctrl = config->execctrl ^ (gpio_base ? ((used >> 20) << (PIO_SM0_EXECCTRL_JMP_PIN_LSB + 4)) : 0);
828 pio->sm[sm].pinctrl = config->pinctrl ^ (gpio_base ? ((used << 12) >> 8) : 0);
829#else
830 pio->sm[sm].execctrl = config->execctrl;
831 pio->sm[sm].pinctrl = config->pinctrl;
832#endif
833 return PICO_OK;
834}
835
842static inline uint pio_get_index(PIO pio) {
843 check_pio_param(pio);
844 return PIO_NUM(pio);
845}
846
854static inline uint pio_get_funcsel(PIO pio) {
855 check_pio_param(pio);
856 return PIO_FUNCSEL_NUM(pio, 0); // note GPIO currently unused, so won't bother updating API
857}
858
865static inline PIO pio_get_instance(uint instance) {
866 invalid_params_if(HARDWARE_PIO, instance >= NUM_PIOS);
867 return PIO_INSTANCE(instance);
868}
869
882static inline void pio_gpio_init(PIO pio, uint pin) {
883 check_pio_param(pio);
884 valid_params_if(HARDWARE_PIO, pin < NUM_BANK0_GPIOS);
885 gpio_set_function(pin, PIO_FUNCSEL_NUM(pio, pin));
886}
887
895static inline uint pio_get_dreq(PIO pio, uint sm, bool is_tx) {
896 check_pio_param(pio);
897 check_sm_param(sm);
898 return PIO_DREQ_NUM(pio, sm, is_tx);
899}
900
901typedef struct pio_program {
902 const uint16_t *instructions;
903 uint8_t length;
904 int8_t origin; // required instruction memory origin or -1
905 uint8_t pio_version;
906#if PICO_PIO_VERSION > 0
907 uint8_t used_gpio_ranges; // bitmap with one bit per 16 pins
908#endif
910
925int pio_set_gpio_base(PIO pio, uint gpio_base);
926
935bool pio_can_add_program(PIO pio, const pio_program_t *program);
936
946bool pio_can_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset);
947
958int pio_add_program(PIO pio, const pio_program_t *program);
959
971int pio_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset);
972
980void pio_remove_program(PIO pio, const pio_program_t *program, uint loaded_offset);
981
988
1011int pio_sm_init(PIO pio, uint sm, uint initial_pc, const pio_sm_config *config);
1012
1020static inline void pio_sm_set_enabled(PIO pio, uint sm, bool enabled) {
1021 check_pio_param(pio);
1022 check_sm_param(sm);
1023 pio->ctrl = (pio->ctrl & ~(1u << sm)) | (bool_to_bit(enabled) << sm);
1024}
1025
1039static inline void pio_set_sm_mask_enabled(PIO pio, uint32_t mask, bool enabled) {
1040 check_pio_param(pio);
1041 check_sm_mask(mask);
1042 pio->ctrl = (pio->ctrl & ~mask) | (enabled ? mask : 0u);
1043}
1044
1045#if PICO_PIO_VERSION > 0
1061static inline void pio_set_sm_multi_mask_enabled(PIO pio, uint32_t mask_prev, uint32_t mask, uint32_t mask_next, bool enabled) {
1062 check_pio_param(pio);
1063 check_sm_mask(mask);
1064 pio->ctrl = (pio->ctrl & ~(mask << PIO_CTRL_SM_ENABLE_LSB)) |
1065 (enabled ? ((mask << PIO_CTRL_SM_ENABLE_LSB) & PIO_CTRL_SM_ENABLE_BITS) : 0) |
1066 (enabled ? PIO_CTRL_NEXTPREV_SM_ENABLE_BITS : PIO_CTRL_NEXTPREV_SM_DISABLE_BITS) |
1067 ((mask_prev << PIO_CTRL_PREV_PIO_MASK_LSB) & PIO_CTRL_PREV_PIO_MASK_BITS) |
1068 ((mask_next << PIO_CTRL_NEXT_PIO_MASK_LSB) & PIO_CTRL_NEXT_PIO_MASK_BITS);
1069
1070}
1071#endif
1072
1082static inline void pio_sm_restart(PIO pio, uint sm) {
1083 check_pio_param(pio);
1084 check_sm_param(sm);
1085 hw_set_bits(&pio->ctrl, 1u << (PIO_CTRL_SM_RESTART_LSB + sm));
1086}
1087
1097static inline void pio_restart_sm_mask(PIO pio, uint32_t mask) {
1098 check_pio_param(pio);
1099 check_sm_mask(mask);
1100 hw_set_bits(&pio->ctrl, (mask << PIO_CTRL_SM_RESTART_LSB) & PIO_CTRL_SM_RESTART_BITS);
1101}
1102
1124static inline void pio_sm_clkdiv_restart(PIO pio, uint sm) {
1125 check_pio_param(pio);
1126 check_sm_param(sm);
1127 hw_set_bits(&pio->ctrl, 1u << (PIO_CTRL_CLKDIV_RESTART_LSB + sm));
1128}
1129
1159static inline void pio_clkdiv_restart_sm_mask(PIO pio, uint32_t mask) {
1160 check_pio_param(pio);
1161 check_sm_mask(mask);
1162 hw_set_bits(&pio->ctrl, (mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS);
1163}
1164
1165#if PICO_PIO_VERSION > 0
1197static inline void pio_clkdiv_restart_sm_multi_mask(PIO pio, uint32_t mask_prev, uint32_t mask, uint32_t mask_next) {
1198 check_pio_param(pio);
1199 check_sm_mask(mask);
1200 hw_set_bits(&pio->ctrl, ((mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS) |
1201 PIO_CTRL_NEXTPREV_CLKDIV_RESTART_BITS |
1202 ((mask_prev << PIO_CTRL_PREV_PIO_MASK_LSB) & PIO_CTRL_PREV_PIO_MASK_BITS) |
1203 ((mask_next << PIO_CTRL_NEXT_PIO_MASK_LSB) & PIO_CTRL_NEXT_PIO_MASK_BITS));
1204}
1205#endif
1206
1218static inline void pio_enable_sm_mask_in_sync(PIO pio, uint32_t mask) {
1219 check_pio_param(pio);
1220 check_sm_mask(mask);
1221 hw_set_bits(&pio->ctrl,
1222 ((mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS) |
1223 ((mask << PIO_CTRL_SM_ENABLE_LSB) & PIO_CTRL_SM_ENABLE_BITS));
1224}
1225
1226#if PICO_PIO_VERSION > 0
1240static inline void pio_enable_sm_multi_mask_in_sync(PIO pio, uint32_t mask_prev, uint32_t mask, uint32_t mask_next) {
1241 check_pio_param(pio);
1242 check_sm_mask(mask);
1243 check_pio_param(pio);
1244 check_sm_mask(mask);
1245 hw_set_bits(&pio->ctrl, ((mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS) |
1246 ((mask << PIO_CTRL_SM_ENABLE_LSB) & PIO_CTRL_SM_ENABLE_BITS) |
1247 PIO_CTRL_NEXTPREV_CLKDIV_RESTART_BITS | PIO_CTRL_NEXTPREV_SM_ENABLE_BITS |
1248 ((mask_prev << PIO_CTRL_PREV_PIO_MASK_LSB) & PIO_CTRL_PREV_PIO_MASK_BITS) |
1249 ((mask_next << PIO_CTRL_NEXT_PIO_MASK_LSB) & PIO_CTRL_NEXT_PIO_MASK_BITS));
1250}
1251#endif
1252
1257 pis_interrupt0 = PIO_INTR_SM0_LSB,
1258 pis_interrupt1 = PIO_INTR_SM1_LSB,
1259 pis_interrupt2 = PIO_INTR_SM2_LSB,
1260 pis_interrupt3 = PIO_INTR_SM3_LSB,
1261#if PICO_PIO_VERSION > 0
1262 pis_interrupt4 = PIO_INTR_SM4_LSB,
1263 pis_interrupt5 = PIO_INTR_SM5_LSB,
1264 pis_interrupt6 = PIO_INTR_SM6_LSB,
1265 pis_interrupt7 = PIO_INTR_SM7_LSB,
1266#endif
1267 pis_sm0_tx_fifo_not_full = PIO_INTR_SM0_TXNFULL_LSB,
1268 pis_sm1_tx_fifo_not_full = PIO_INTR_SM1_TXNFULL_LSB,
1269 pis_sm2_tx_fifo_not_full = PIO_INTR_SM2_TXNFULL_LSB,
1270 pis_sm3_tx_fifo_not_full = PIO_INTR_SM3_TXNFULL_LSB,
1271 pis_sm0_rx_fifo_not_empty = PIO_INTR_SM0_RXNEMPTY_LSB,
1272 pis_sm1_rx_fifo_not_empty = PIO_INTR_SM1_RXNEMPTY_LSB,
1273 pis_sm2_rx_fifo_not_empty = PIO_INTR_SM2_RXNEMPTY_LSB,
1274 pis_sm3_rx_fifo_not_empty = PIO_INTR_SM3_RXNEMPTY_LSB,
1276
1284static inline void pio_set_irq0_source_enabled(PIO pio, pio_interrupt_source_t source, bool enabled) {
1285 check_pio_param(pio);
1286 invalid_params_if(HARDWARE_PIO, source >= 32u || (1u << source) > PIO_INTR_BITS);
1287 if (enabled)
1288 hw_set_bits(&pio->inte0, 1u << source);
1289 else
1290 hw_clear_bits(&pio->inte0, 1u << source);
1291}
1292
1300static inline void pio_set_irq1_source_enabled(PIO pio, pio_interrupt_source_t source, bool enabled) {
1301 check_pio_param(pio);
1302 invalid_params_if(HARDWARE_PIO, source >= 32 || (1u << source) > PIO_INTR_BITS);
1303 if (enabled)
1304 hw_set_bits(&pio->inte1, 1u << source);
1305 else
1306 hw_clear_bits(&pio->inte1, 1u << source);
1307}
1308
1316static inline void pio_set_irq0_source_mask_enabled(PIO pio, uint32_t source_mask, bool enabled) {
1317 check_pio_param(pio);
1318 invalid_params_if(HARDWARE_PIO, source_mask > PIO_INTR_BITS);
1319 if (enabled) {
1320 hw_set_bits(&pio->inte0, source_mask);
1321 } else {
1322 hw_clear_bits(&pio->inte0, source_mask);
1323 }
1324}
1325
1333static inline void pio_set_irq1_source_mask_enabled(PIO pio, uint32_t source_mask, bool enabled) {
1334 check_pio_param(pio);
1335 invalid_params_if(HARDWARE_PIO, source_mask > PIO_INTR_BITS);
1336 if (enabled) {
1337 hw_set_bits(&pio->inte1, source_mask);
1338 } else {
1339 hw_clear_bits(&pio->inte1, source_mask);
1340 }
1341}
1342
1351static inline void pio_set_irqn_source_enabled(PIO pio, uint irq_index, pio_interrupt_source_t source, bool enabled) {
1352 invalid_params_if(HARDWARE_PIO, irq_index > NUM_PIO_IRQS);
1353 invalid_params_if(HARDWARE_PIO, source >= 32 || (1u << source) > PIO_INTR_BITS);
1354 if (enabled)
1355 hw_set_bits(&pio->irq_ctrl[irq_index].inte, 1u << source);
1356 else
1357 hw_clear_bits(&pio->irq_ctrl[irq_index].inte, 1u << source);
1358}
1359
1368static inline void pio_set_irqn_source_mask_enabled(PIO pio, uint irq_index, uint32_t source_mask, bool enabled) {
1369 invalid_params_if(HARDWARE_PIO, irq_index > NUM_PIO_IRQS);
1370 static_assert(NUM_PIO_IRQS == 2, "");
1371 invalid_params_if(HARDWARE_PIO, source_mask > PIO_INTR_BITS);
1372 if (enabled) {
1373 hw_set_bits(&pio->irq_ctrl[irq_index].inte, source_mask);
1374 } else {
1375 hw_clear_bits(&pio->irq_ctrl[irq_index].inte, source_mask);
1376 }
1377}
1378
1386static inline bool pio_interrupt_get(PIO pio, uint pio_interrupt_num) {
1387 check_pio_param(pio);
1388 invalid_params_if(HARDWARE_PIO, pio_interrupt_num >= 8);
1389 return pio->irq & (1u << pio_interrupt_num);
1390}
1391
1398static inline void pio_interrupt_clear(PIO pio, uint pio_interrupt_num) {
1399 check_pio_param(pio);
1400 invalid_params_if(HARDWARE_PIO, pio_interrupt_num >= 8);
1401 pio->irq = (1u << pio_interrupt_num);
1402}
1403
1411static inline uint8_t pio_sm_get_pc(PIO pio, uint sm) {
1412 check_pio_param(pio);
1413 check_sm_param(sm);
1414 return (uint8_t) pio->sm[sm].addr;
1415}
1416
1429inline static void pio_sm_exec(PIO pio, uint sm, uint instr) {
1430 check_pio_param(pio);
1431 check_sm_param(sm);
1432 pio->sm[sm].instr = instr;
1433}
1434
1442static inline bool pio_sm_is_exec_stalled(PIO pio, uint sm) {
1443 check_pio_param(pio);
1444 check_sm_param(sm);
1445 return pio->sm[sm].execctrl & PIO_SM0_EXECCTRL_EXEC_STALLED_BITS;
1446}
1447
1460static inline void pio_sm_exec_wait_blocking(PIO pio, uint sm, uint instr) {
1461 check_pio_param(pio);
1462 check_sm_param(sm);
1463 pio_sm_exec(pio, sm, instr);
1465}
1466
1476static inline void pio_sm_set_wrap(PIO pio, uint sm, uint wrap_target, uint wrap) {
1477 check_pio_param(pio);
1478 check_sm_param(sm);
1479 valid_params_if(HARDWARE_PIO, wrap < PIO_INSTRUCTION_COUNT);
1480 valid_params_if(HARDWARE_PIO, wrap_target < PIO_INSTRUCTION_COUNT);
1481 pio->sm[sm].execctrl =
1482 (pio->sm[sm].execctrl & ~(PIO_SM0_EXECCTRL_WRAP_TOP_BITS | PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS)) |
1483 (wrap_target << PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB) |
1484 (wrap << PIO_SM0_EXECCTRL_WRAP_TOP_LSB);
1485}
1486
1497static inline void pio_sm_set_out_pins(PIO pio, uint sm, uint out_base, uint out_count) {
1498 check_pio_param(pio);
1499 check_sm_param(sm);
1500#if PICO_PIO_USE_GPIO_BASE
1501 out_base -= pio_get_gpio_base(pio);
1502#endif
1503 valid_params_if(HARDWARE_PIO, out_base < 32);
1504 valid_params_if(HARDWARE_PIO, out_count <= 32);
1505 pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~(PIO_SM0_PINCTRL_OUT_BASE_BITS | PIO_SM0_PINCTRL_OUT_COUNT_BITS)) |
1506 (out_base << PIO_SM0_PINCTRL_OUT_BASE_LSB) |
1507 (out_count << PIO_SM0_PINCTRL_OUT_COUNT_LSB);
1508}
1509
1510
1521static inline void pio_sm_set_set_pins(PIO pio, uint sm, uint set_base, uint set_count) {
1522 check_pio_param(pio);
1523 check_sm_param(sm);
1524#if PICO_PIO_USE_GPIO_BASE
1525 set_base -= pio_get_gpio_base(pio);
1526#endif
1527 valid_params_if(HARDWARE_PIO, set_base < 32);
1528 valid_params_if(HARDWARE_PIO, set_count <= 5);
1529 pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~(PIO_SM0_PINCTRL_SET_BASE_BITS | PIO_SM0_PINCTRL_SET_COUNT_BITS)) |
1530 (set_base << PIO_SM0_PINCTRL_SET_BASE_LSB) |
1531 (set_count << PIO_SM0_PINCTRL_SET_COUNT_LSB);
1532}
1533
1543static inline void pio_sm_set_in_pins(PIO pio, uint sm, uint in_base) {
1544 check_pio_param(pio);
1545 check_sm_param(sm);
1546#if PICO_PIO_USE_GPIO_BASE
1547 in_base -= pio_get_gpio_base(pio);
1548#endif
1549 valid_params_if(HARDWARE_PIO, in_base < 32);
1550 pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~PIO_SM0_PINCTRL_IN_BASE_BITS) |
1551 (in_base << PIO_SM0_PINCTRL_IN_BASE_LSB);
1552}
1553
1563static inline void pio_sm_set_sideset_pins(PIO pio, uint sm, uint sideset_base) {
1564 check_pio_param(pio);
1565 check_sm_param(sm);
1566#if PICO_PIO_USE_GPIO_BASE
1567 sideset_base -= pio_get_gpio_base(pio);
1568#endif
1569 valid_params_if(HARDWARE_PIO, sideset_base < 32);
1570 pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~PIO_SM0_PINCTRL_SIDESET_BASE_BITS) |
1571 (sideset_base << PIO_SM0_PINCTRL_SIDESET_BASE_LSB);
1572}
1573
1582static inline void pio_sm_set_jmp_pin(PIO pio, uint sm, uint pin) {
1583 check_pio_param(pio);
1584 check_sm_param(sm);
1585#if PICO_PIO_USE_GPIO_BASE
1586 pin -= pio_get_gpio_base(pio);
1587#endif
1588 valid_params_if(HARDWARE_PIO, pin < 32);
1589 pio->sm[sm].execctrl =
1590 (pio->sm[sm].execctrl & ~PIO_SM0_EXECCTRL_JMP_PIN_BITS)
1591 | (pin << PIO_SM0_EXECCTRL_JMP_PIN_LSB);
1592}
1593
1608static inline void pio_sm_put(PIO pio, uint sm, uint32_t data) {
1609 check_pio_param(pio);
1610 check_sm_param(sm);
1611 pio->txf[sm] = data;
1612}
1613
1629static inline uint32_t pio_sm_get(PIO pio, uint sm) {
1630 check_pio_param(pio);
1631 check_sm_param(sm);
1632 return pio->rxf[sm];
1633}
1634
1642static inline bool pio_sm_is_rx_fifo_full(PIO pio, uint sm) {
1643 check_pio_param(pio);
1644 check_sm_param(sm);
1645 return (pio->fstat & (1u << (PIO_FSTAT_RXFULL_LSB + sm))) != 0;
1646}
1647
1655static inline bool pio_sm_is_rx_fifo_empty(PIO pio, uint sm) {
1656 check_pio_param(pio);
1657 check_sm_param(sm);
1658 return (pio->fstat & (1u << (PIO_FSTAT_RXEMPTY_LSB + sm))) != 0;
1659}
1660
1668static inline uint pio_sm_get_rx_fifo_level(PIO pio, uint sm) {
1669 check_pio_param(pio);
1670 check_sm_param(sm);
1671 uint bitoffs = PIO_FLEVEL_RX0_LSB + sm * (PIO_FLEVEL_RX1_LSB - PIO_FLEVEL_RX0_LSB);
1672 const uint32_t mask = PIO_FLEVEL_RX0_BITS >> PIO_FLEVEL_RX0_LSB;
1673 return (pio->flevel >> bitoffs) & mask;
1674}
1675
1683static inline bool pio_sm_is_tx_fifo_full(PIO pio, uint sm) {
1684 check_pio_param(pio);
1685 check_sm_param(sm);
1686 return (pio->fstat & (1u << (PIO_FSTAT_TXFULL_LSB + sm))) != 0;
1687}
1688
1696static inline bool pio_sm_is_tx_fifo_empty(PIO pio, uint sm) {
1697 check_pio_param(pio);
1698 check_sm_param(sm);
1699 return (pio->fstat & (1u << (PIO_FSTAT_TXEMPTY_LSB + sm))) != 0;
1700}
1701
1709static inline uint pio_sm_get_tx_fifo_level(PIO pio, uint sm) {
1710 check_pio_param(pio);
1711 check_sm_param(sm);
1712 unsigned int bitoffs = PIO_FLEVEL_TX0_LSB + sm * (PIO_FLEVEL_TX1_LSB - PIO_FLEVEL_TX0_LSB);
1713 const uint32_t mask = PIO_FLEVEL_TX0_BITS >> PIO_FLEVEL_TX0_LSB;
1714 return (pio->flevel >> bitoffs) & mask;
1715}
1716
1724static inline void pio_sm_put_blocking(PIO pio, uint sm, uint32_t data) {
1725 check_pio_param(pio);
1726 check_sm_param(sm);
1728 pio_sm_put(pio, sm, data);
1729}
1730
1737static inline uint32_t pio_sm_get_blocking(PIO pio, uint sm) {
1738 check_pio_param(pio);
1739 check_sm_param(sm);
1741 return pio_sm_get(pio, sm);
1742}
1743
1757void pio_sm_drain_tx_fifo(PIO pio, uint sm);
1758
1767static inline void pio_sm_set_clkdiv_int_frac8(PIO pio, uint sm, uint32_t div_int, uint8_t div_frac8) {
1768 check_pio_param(pio);
1769 check_sm_param(sm);
1770 static_assert(REG_FIELD_WIDTH(PIO_SM0_CLKDIV_INT) == 16, "");
1771 invalid_params_if(HARDWARE_PIO, div_int >> 16);
1772 invalid_params_if(HARDWARE_PIO, div_int == 0 && div_frac8 != 0);
1773 static_assert(REG_FIELD_WIDTH(PIO_SM0_CLKDIV_FRAC) == 8, "");
1774 pio->sm[sm].clkdiv =
1775 (((uint)div_frac8) << PIO_SM0_CLKDIV_FRAC_LSB) |
1776 (((uint)div_int) << PIO_SM0_CLKDIV_INT_LSB);
1777}
1778
1779// backwards compatibility
1780static inline void pio_sm_set_clkdiv_int_frac(PIO pio, uint sm, uint16_t div_int, uint8_t div_frac8) {
1781 pio_sm_set_clkdiv_int_frac8(pio, sm, div_int, div_frac8);
1782}
1783
1791static inline void pio_sm_set_clkdiv(PIO pio, uint sm, float div) {
1792 check_pio_param(pio);
1793 check_sm_param(sm);
1794 uint32_t div_int;
1795 uint8_t div_frac8;
1796 pio_calculate_clkdiv8_from_float(div, &div_int, &div_frac8);
1797 pio_sm_set_clkdiv_int_frac8(pio, sm, div_int, div_frac8);
1798}
1799
1806static inline void pio_sm_clear_fifos(PIO pio, uint sm) {
1807 // changing the FIFO join state clears the fifo
1808 check_pio_param(pio);
1809 check_sm_param(sm);
1810 hw_xor_bits(&pio->sm[sm].shiftctrl, PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS);
1811 hw_xor_bits(&pio->sm[sm].shiftctrl, PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS);
1812}
1813
1827void pio_sm_set_pins(PIO pio, uint sm, uint32_t pin_values);
1828
1841void pio_sm_set_pins64(PIO pio, uint sm, uint64_t pin_values);
1842
1857void pio_sm_set_pins_with_mask(PIO pio, uint sm, uint32_t pin_values, uint32_t pin_mask);
1858
1872void pio_sm_set_pins_with_mask64(PIO pio, uint sm, uint64_t pin_values, uint64_t pin_mask);
1873
1888void pio_sm_set_pindirs_with_mask(PIO pio, uint sm, uint32_t pin_dirs, uint32_t pin_mask);
1889
1903void pio_sm_set_pindirs_with_mask64(PIO pio, uint sm, uint64_t pin_dirs, uint64_t pin_mask);
1904
1920int pio_sm_set_consecutive_pindirs(PIO pio, uint sm, uint pins_base, uint pin_count, bool is_out);
1921
1932void pio_sm_claim(PIO pio, uint sm);
1933
1944void pio_claim_sm_mask(PIO pio, uint sm_mask);
1945
1954void pio_sm_unclaim(PIO pio, uint sm);
1955
1964int pio_claim_unused_sm(PIO pio, bool required);
1965
1975bool pio_sm_is_claimed(PIO pio, uint sm);
1976
1987bool pio_claim_free_sm_and_add_program(const pio_program_t *program, PIO *pio, uint *sm, uint *offset);
1988
2011bool pio_claim_free_sm_and_add_program_for_gpio_range(const pio_program_t *program, PIO *pio, uint *sm, uint *offset, uint gpio_base, uint gpio_count, bool set_gpio_base);
2012
2022void pio_remove_program_and_unclaim_sm(const pio_program_t *program, PIO pio, uint sm, uint offset);
2023
2031static inline int pio_get_irq_num(PIO pio, uint irqn) {
2032 check_pio_param(pio);
2033 valid_params_if(HARDWARE_PIO, irqn < NUM_PIO_IRQS);
2034 return PIO_IRQ_NUM(pio, irqn);
2035}
2036
2044 check_sm_param(sm);
2046}
2047
2055 check_sm_param(sm);
2057}
2058
2059#ifdef __cplusplus
2060}
2061#endif
2062
2063#endif // _PIO_H_
static __force_inline void hw_set_bits(io_rw_32 *addr, uint32_t mask)
Atomically set the specified bits to 1 in a HW register.
Definition address_mapped.h:135
static __force_inline void hw_xor_bits(io_rw_32 *addr, uint32_t mask)
Atomically flip the specified bits in a HW register.
Definition address_mapped.h:155
static __force_inline void hw_clear_bits(io_rw_32 *addr, uint32_t mask)
Atomically clear the specified bits to 0 in a HW register.
Definition address_mapped.h:145
@ DREQ_PIO0_TX3
Select PIO0's TX FIFO 3 as DREQ.
Definition dreq.h:70
@ DREQ_PIO1_TX0
Select PIO1's TX FIFO 0 as DREQ.
Definition dreq.h:75
@ DREQ_PIO1_RX0
Select PIO1's RX FIFO 0 as DREQ.
Definition dreq.h:79
@ DREQ_PIO0_TX2
Select PIO0's TX FIFO 2 as DREQ.
Definition dreq.h:69
@ DREQ_PIO0_RX0
Select PIO0's RX FIFO 0 as DREQ.
Definition dreq.h:71
@ DREQ_PIO0_TX1
Select PIO0's TX FIFO 1 as DREQ.
Definition dreq.h:68
@ DREQ_PIO0_TX0
Select PIO0's TX FIFO 0 as DREQ.
Definition dreq.h:67
void gpio_set_function(uint gpio, gpio_function_t fn)
Select GPIO function.
Definition gpio.c:38
static uint pio_sm_get_tx_fifo_level(PIO pio, uint sm)
Return the number of elements currently in a state machine's TX FIFO.
Definition pio.h:1709
bool pio_claim_free_sm_and_add_program(const pio_program_t *program, PIO *pio, uint *sm, uint *offset)
Finds a PIO and statemachine and adds a program into PIO memory.
Definition pio.c:404
#define PIO_INSTANCE(instance)
Returns the PIO instance with the given PIO number.
Definition pio.h:194
static void pio_set_irqn_source_enabled(PIO pio, uint irq_index, pio_interrupt_source_t source, bool enabled)
Enable/Disable a single source on a PIO's specified (0/1) IRQ index.
Definition pio.h:1351
void pio_sm_set_pins_with_mask64(PIO pio, uint sm, uint64_t pin_values, uint64_t pin_mask)
Use a state machine to set a value on multiple pins for the PIO instance.
Definition pio.c:298
pio_interrupt_source
PIO interrupt source numbers for pio related IRQs.
Definition pio.h:1256
static uint32_t pio_sm_get_blocking(PIO pio, uint sm)
Read a word of data from a state machine's RX FIFO, blocking if the FIFO is empty.
Definition pio.h:1737
void pio_sm_set_pins(PIO pio, uint sm, uint32_t pin_values)
Use a state machine to set a value on all pins for the PIO instance.
Definition pio.c:230
int pio_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset)
Attempt to load the program at the specified instruction memory offset.
Definition pio.c:192
static void pio_sm_set_clkdiv_int_frac8(PIO pio, uint sm, uint32_t div_int, uint8_t div_frac8)
set the current clock divider for a state machine using a 16:8 fraction
Definition pio.h:1767
static PIO pio_get_instance(uint instance)
Convert PIO instance to hardware instance.
Definition pio.h:865
static void pio_sm_exec_wait_blocking(PIO pio, uint sm, uint instr)
Immediately execute an instruction on a state machine and wait for it to complete.
Definition pio.h:1460
static int pio_sm_set_config(PIO pio, uint sm, const pio_sm_config *config)
Apply a state machine configuration to a state machine.
Definition pio.h:809
static int pio_get_irq_num(PIO pio, uint irqn)
Return an IRQ for a PIO hardware instance.
Definition pio.h:2031
int pio_set_gpio_base(PIO pio, uint gpio_base)
Set the base GPIO base for the PIO instance.
Definition pio.c:97
pio_mov_status_type
MOV status types.
Definition pio.h:122
static bool pio_sm_is_tx_fifo_full(PIO pio, uint sm)
Determine if a state machine's TX FIFO is full.
Definition pio.h:1683
static uint pio_get_dreq(PIO pio, uint sm, bool is_tx)
Return the DREQ to use for pacing transfers to/from a particular state machine FIFO.
Definition pio.h:895
static void pio_set_irq1_source_enabled(PIO pio, pio_interrupt_source_t source, bool enabled)
Enable/Disable a single source on a PIO's IRQ 1.
Definition pio.h:1300
void pio_sm_set_pindirs_with_mask64(PIO pio, uint sm, uint64_t pin_dirs, uint64_t pin_mask)
Use a state machine to set the pin directions for multiple pins for the PIO instance.
Definition pio.c:335
void pio_sm_drain_tx_fifo(PIO pio, uint sm)
Empty out a state machine's TX FIFO.
Definition pio.c:396
void pio_claim_sm_mask(PIO pio, uint sm_mask)
Mark multiple state machines as used.
Definition pio.c:36
bool pio_claim_free_sm_and_add_program_for_gpio_range(const pio_program_t *program, PIO *pio, uint *sm, uint *offset, uint gpio_base, uint gpio_count, bool set_gpio_base)
Finds a PIO and statemachine and adds a program into PIO memory.
Definition pio.c:408
void pio_sm_set_pins64(PIO pio, uint sm, uint64_t pin_values)
Use a state machine to set a value on all pins for the PIO instance.
Definition pio.c:261
int pio_claim_unused_sm(PIO pio, bool required)
Claim a free state machine on a PIO instance.
Definition pio.c:48
void pio_sm_unclaim(PIO pio, uint sm)
Mark a state machine as no longer used.
Definition pio.c:42
static void pio_clkdiv_restart_sm_mask(PIO pio, uint32_t mask)
Restart multiple state machines' clock dividers from a phase of 0.
Definition pio.h:1159
bool pio_sm_is_claimed(PIO pio, uint sm)
Determine if a PIO state machine is claimed.
Definition pio.c:57
static void pio_interrupt_clear(PIO pio, uint pio_interrupt_num)
Clear a particular PIO interrupt.
Definition pio.h:1398
static uint32_t pio_sm_get(PIO pio, uint sm)
Read a word of data from a state machine's RX FIFO.
Definition pio.h:1629
static bool pio_sm_is_rx_fifo_full(PIO pio, uint sm)
Determine if a state machine's RX FIFO is full.
Definition pio.h:1642
static void pio_sm_set_wrap(PIO pio, uint sm, uint wrap_target, uint wrap)
Set the current wrap configuration for a state machine.
Definition pio.h:1476
#define PIO_NUM(pio)
Returns the PIO number for a PIO instance.
Definition pio.h:178
static void pio_sm_restart(PIO pio, uint sm)
Restart a state machine with a known state.
Definition pio.h:1082
pio_fifo_join
FIFO join states.
Definition pio.h:108
static void pio_sm_set_out_pins(PIO pio, uint sm, uint out_base, uint out_count)
Set the current 'out' pins for a state machine.
Definition pio.h:1497
static void pio_sm_exec(PIO pio, uint sm, uint instr)
Immediately execute an instruction on a state machine.
Definition pio.h:1429
static void pio_set_irq0_source_mask_enabled(PIO pio, uint32_t source_mask, bool enabled)
Enable/Disable multiple sources on a PIO's IRQ 0.
Definition pio.h:1316
void pio_remove_program(PIO pio, const pio_program_t *program, uint loaded_offset)
Remove a program from a PIO instance's instruction memory.
Definition pio.c:199
void pio_sm_set_pindirs_with_mask(PIO pio, uint sm, uint32_t pin_dirs, uint32_t pin_mask)
Use a state machine to set the pin directions for multiple pins for the PIO instance.
Definition pio.c:307
void pio_clear_instruction_memory(PIO pio)
Clears all of a PIO instance's instruction memory.
Definition pio.c:208
static void pio_sm_set_sideset_pins(PIO pio, uint sm, uint sideset_base)
Set the current 'sideset' pins for a state machine.
Definition pio.h:1563
static void pio_sm_set_clkdiv(PIO pio, uint sm, float div)
set the current clock divider for a state machine
Definition pio.h:1791
static uint pio_get_gpio_base(PIO pio)
Return the base GPIO base for the PIO instance.
Definition pio.h:780
static pio_interrupt_source_t pio_get_tx_fifo_not_full_interrupt_source(uint sm)
Return the interrupt source for a state machines TX FIFO not full interrupt.
Definition pio.h:2043
static uint pio_sm_get_rx_fifo_level(PIO pio, uint sm)
Return the number of elements currently in a state machine's RX FIFO.
Definition pio.h:1668
#define pio0
Definition pio.h:138
#define pio1
Definition pio.h:146
void pio_sm_set_pins_with_mask(PIO pio, uint sm, uint32_t pin_values, uint32_t pin_mask)
Use a state machine to set a value on multiple pins for the PIO instance.
Definition pio.c:270
static void pio_sm_set_jmp_pin(PIO pio, uint sm, uint pin)
Set the 'jmp' pin for a state machine.
Definition pio.h:1582
static uint8_t pio_sm_get_pc(PIO pio, uint sm)
Return the current program counter for a state machine.
Definition pio.h:1411
static uint pio_get_funcsel(PIO pio)
Return the funcsel number of a PIO instance.
Definition pio.h:854
#define PIO_FUNCSEL_NUM(pio, gpio)
Returns gpio_function_t needed to select the PIO function for the given PIO instance on the given GPI...
Definition pio.h:206
static void pio_sm_set_enabled(PIO pio, uint sm, bool enabled)
Enable or disable a PIO state machine.
Definition pio.h:1020
void pio_sm_claim(PIO pio, uint sm)
Mark a state machine as used.
Definition pio.c:24
void pio_remove_program_and_unclaim_sm(const pio_program_t *program, PIO pio, uint sm, uint offset)
Removes a program from PIO memory and unclaims the state machine.
Definition pio.c:464
bool pio_can_add_program(PIO pio, const pio_program_t *program)
Determine whether the given program can (at the time of the call) be loaded onto the PIO instance.
Definition pio.c:145
static bool pio_interrupt_get(PIO pio, uint pio_interrupt_num)
Determine if a particular PIO interrupt is set.
Definition pio.h:1386
static bool pio_sm_is_exec_stalled(PIO pio, uint sm)
Determine if an instruction set by pio_sm_exec() is stalled executing.
Definition pio.h:1442
bool pio_can_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset)
Determine whether the given program can (at the time of the call) be loaded onto the PIO instance sta...
Definition pio.c:153
static void pio_sm_put(PIO pio, uint sm, uint32_t data)
Write a word of data to a state machine's TX FIFO.
Definition pio.h:1608
static void pio_sm_clear_fifos(PIO pio, uint sm)
Clear a state machine's TX and RX FIFOs.
Definition pio.h:1806
enum pio_interrupt_source pio_interrupt_source_t
PIO interrupt source numbers for pio related IRQs.
#define PIO_DREQ_NUM(pio, sm, is_tx)
Returns the dreq_num_t used for pacing DMA transfers to or from a given state machine's FIFOs on this...
Definition pio.h:229
static void pio_enable_sm_mask_in_sync(PIO pio, uint32_t mask)
Enable multiple PIO state machines synchronizing their clock dividers.
Definition pio.h:1218
static void pio_sm_set_set_pins(PIO pio, uint sm, uint set_base, uint set_count)
Set the current 'set' pins for a state machine.
Definition pio.h:1521
static void pio_sm_clkdiv_restart(PIO pio, uint sm)
Restart a state machine's clock divider from a phase of 0.
Definition pio.h:1124
static pio_interrupt_source_t pio_get_rx_fifo_not_empty_interrupt_source(uint sm)
Return the interrupt source for a state machines RX FIFO not empty interrupt.
Definition pio.h:2054
static bool pio_sm_is_rx_fifo_empty(PIO pio, uint sm)
Determine if a state machine's RX FIFO is empty.
Definition pio.h:1655
static bool pio_sm_is_tx_fifo_empty(PIO pio, uint sm)
Determine if a state machine's TX FIFO is empty.
Definition pio.h:1696
static void pio_set_irq1_source_mask_enabled(PIO pio, uint32_t source_mask, bool enabled)
Enable/Disable multiple sources on a PIO's IRQ 1.
Definition pio.h:1333
static void pio_restart_sm_mask(PIO pio, uint32_t mask)
Restart multiple state machine with a known state.
Definition pio.h:1097
static uint pio_get_index(PIO pio)
Return the instance number of a PIO instance.
Definition pio.h:842
#define PIO_IRQ_NUM(pio, irqn)
Returns the irq_num_t for processor interrupts from the given PIO instance.
Definition pio.h:241
static void pio_sm_put_blocking(PIO pio, uint sm, uint32_t data)
Write a word of data to a state machine's TX FIFO, blocking if the FIFO is full.
Definition pio.h:1724
static void pio_sm_set_in_pins(PIO pio, uint sm, uint in_base)
Set the current 'in' pins for a state machine.
Definition pio.h:1543
int pio_add_program(PIO pio, const pio_program_t *program)
Attempt to load the program.
Definition pio.c:182
int pio_sm_set_consecutive_pindirs(PIO pio, uint sm, uint pins_base, uint pin_count, bool is_out)
Use a state machine to set the same pin direction for multiple consecutive pins for the PIO instance.
Definition pio.c:343
static void pio_set_sm_mask_enabled(PIO pio, uint32_t mask, bool enabled)
Enable or disable multiple PIO state machines.
Definition pio.h:1039
static void pio_gpio_init(PIO pio, uint pin)
Setup the function select for a GPIO to use output from the given PIO instance.
Definition pio.h:882
static void pio_set_irqn_source_mask_enabled(PIO pio, uint irq_index, uint32_t source_mask, bool enabled)
Enable/Disable multiple sources on a PIO's specified (0/1) IRQ index.
Definition pio.h:1368
static void pio_set_irq0_source_enabled(PIO pio, pio_interrupt_source_t source, bool enabled)
Enable/Disable a single source on a PIO's IRQ 0.
Definition pio.h:1284
@ pis_interrupt2
PIO interrupt 2 is raised.
Definition pio.h:1259
@ pis_sm2_tx_fifo_not_full
State machine 2 TX FIFO is not full.
Definition pio.h:1269
@ pis_interrupt0
PIO interrupt 0 is raised.
Definition pio.h:1257
@ pis_sm1_tx_fifo_not_full
State machine 1 TX FIFO is not full.
Definition pio.h:1268
@ pis_sm3_tx_fifo_not_full
State machine 3 TX FIFO is not full.
Definition pio.h:1270
@ pis_interrupt1
PIO interrupt 1 is raised.
Definition pio.h:1258
@ pis_sm2_rx_fifo_not_empty
State machine 2 RX FIFO is not empty.
Definition pio.h:1273
@ pis_sm1_rx_fifo_not_empty
State machine 1 RX FIFO is not empty.
Definition pio.h:1272
@ pis_sm0_tx_fifo_not_full
State machine 0 TX FIFO is not full.
Definition pio.h:1267
@ pis_interrupt3
PIO interrupt 3 is raised.
Definition pio.h:1260
@ pis_sm0_rx_fifo_not_empty
State machine 0 RX FIFO is not empty.
Definition pio.h:1271
@ pis_sm3_rx_fifo_not_empty
State machine 3 RX FIFO is not empty.
Definition pio.h:1274
@ PIO_FIFO_JOIN_NONE
TX FIFO length=4 is used for transmit, RX FIFO length=4 is used for receive.
Definition pio.h:109
@ PIO_FIFO_JOIN_TX
TX FIFO length=8 is used for transmit, RX FIFO is disabled.
Definition pio.h:110
@ PIO_FIFO_JOIN_RX
RX FIFO length=8 is used for receive, TX FIFO is disabled.
Definition pio.h:111
@ PICO_OK
No error; the operation succeeded.
Definition error.h:23
@ PICO_ERROR_BAD_ALIGNMENT
Address was mis-aligned (usually not on word boundary)
Definition error.h:35
static __force_inline void tight_loop_contents(void)
No-op function for the body of tight loops.
Definition platform.h:91
static void sm_config_set_out_pin_base(pio_sm_config *c, uint out_base)
Set the base of the 'out' pins in a state machine configuration.
Definition pio.h:345
static void sm_config_set_out_special(pio_sm_config *c, bool sticky, bool has_enable_pin, uint enable_bit_index)
Set special 'out' operations in a state machine configuration.
Definition pio.h:710
static void sm_config_set_set_pin_base(pio_sm_config *c, uint set_base)
Set the base of the 'set' pins in a state machine configuration.
Definition pio.h:391
static void sm_config_set_in_pin_count(pio_sm_config *c, uint in_count)
Set the count of 'in' pins in a state machine configuration.
Definition pio.h:472
static void sm_config_set_out_shift(pio_sm_config *c, bool shift_right, bool autopull, uint pull_threshold)
Setup 'out' shifting parameters in a state machine configuration.
Definition pio.h:668
static void sm_config_set_set_pin_count(pio_sm_config *c, uint set_count)
Set the count of 'set' pins in a state machine configuration.
Definition pio.h:409
static void sm_config_set_sideset_pin_base(pio_sm_config *c, uint sideset_base)
Set the base of the 'sideset' pins in a state machine configuration.
Definition pio.h:492
static void sm_config_set_clkdiv_int_frac8(pio_sm_config *c, uint32_t div_int, uint8_t div_frac8)
Set the state machine clock divider (from integer and fractional parts - 16:8) in a state machine con...
Definition pio.h:548
static void sm_config_set_in_pin_base(pio_sm_config *c, uint in_base)
Set the base of the 'in' pins in a state machine configuration.
Definition pio.h:437
static void sm_config_set_in_pins(pio_sm_config *c, uint in_base)
Set the base for the 'in' pins in a state machine configuration.
Definition pio.h:455
static void sm_config_set_mov_status(pio_sm_config *c, enum pio_mov_status_type status_sel, uint status_n)
Set source for 'mov status' in a state machine configuration.
Definition pio.h:726
static void sm_config_set_sideset_pins(pio_sm_config *c, uint sideset_base)
Set the 'sideset' pins in a state machine configuration.
Definition pio.h:513
static void sm_config_set_set_pins(pio_sm_config *c, uint set_base, uint set_count)
Set the 'set' pins in a state machine configuration.
Definition pio.h:424
static void sm_config_set_out_pin_count(pio_sm_config *c, uint out_count)
Set the number of 'out' pins in a state machine configuration.
Definition pio.h:363
static void sm_config_set_clkdiv(pio_sm_config *c, float div)
Set the state machine clock divider (from a floating point value) in a state machine configuration.
Definition pio.h:602
static void sm_config_set_in_shift(pio_sm_config *c, bool shift_right, bool autopush, uint push_threshold)
Setup 'in' shifting parameters in a state machine configuration.
Definition pio.h:649
static void sm_config_set_jmp_pin(pio_sm_config *c, uint pin)
Set the 'jmp' pin in a state machine configuration.
Definition pio.h:631
static pio_sm_config pio_get_default_sm_config(void)
Get the default state machine configuration.
Definition pio.h:758
static void sm_config_set_out_pins(pio_sm_config *c, uint out_base, uint out_count)
Set the 'out' pins in a state machine configuration.
Definition pio.h:378
static void sm_config_set_sideset(pio_sm_config *c, uint bit_count, bool optional, bool pindirs)
Set the 'sideset' options in a state machine configuration.
Definition pio.h:525
static void sm_config_set_wrap(pio_sm_config *c, uint wrap_target, uint wrap)
Set the wrap addresses in a state machine configuration.
Definition pio.h:617
static void sm_config_set_fifo_join(pio_sm_config *c, enum pio_fifo_join join)
Setup the FIFO joining in a state machine configuration.
Definition pio.h:685
Definition pio.h:132
Definition pio.h:901
PIO Configuration structure.
Definition pio.h:290